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1.5MHz, 30A High-Efficiency, LED Driver
with Rapid LED Current Pulsing
Inductor Current-Sense Amplifier
The differential current-sense amplifier (CA) provides a
DC gain of 34.5. The maximum input offset voltage of
the current-sense amplifier is 1mV and the common-
mode voltage range is 0 to 5.5V (IN = 7V to 28V). The
current-sense amplifier senses the voltage across a
current-sense resistor. The maximum common-mode
voltage is 3.6V when V IN = 5V.
Inductor Peak-Current Comparator
The peak-current comparator provides a path for fast
cycle-by-cycle current limit during extreme fault condi-
tions, such as an inductor malfunction (Figure 8). Note
the average current-limit threshold of 26.9mV still limits
the output current during short-circuit conditions. To
prevent inductor saturation, select an inductor with a
saturation current specification greater than the average
current limit. Proper inductor selection ensures that only
the extreme conditions trip the peak-current comparator,
such as an inductor with a shorted turn. The 60mV
threshold for triggering the peak-current limit is twice the
full-scale average current-limit voltage threshold. The
Current-Error Amplifier
(For Inductor Currents)
The MAX16818 has a transconductance current-error
amplifier (CEA) with a typical g m of 550μS and 320μA
output sink- and source-current capability. The current-
error amplifier output CLP serves as the inverting input
to the PWM comparator. CLP is externally accessible to
provide frequency compensation for the inner current
loops (Figure 7). Compensate (CEA) so the inductor
current negative slope, which becomes the positive
slope to the inverting input of the PWM comparator, is
less than the slope of the internally generated voltage
ramp (see the Compensation section).
PWM Comparator and R-S Flip-Flop
The PWM comparator (CPWM) sets the duty cycle for
each cycle by comparing the output of the current-error
amplifier to a 2V P-P ramp. At the start of each clock
cycle, an R-S flip-flop resets and the high-side driver
(DH) goes high. The comparator sets the flip-flop as
soon as the ramp voltage exceeds the CLP voltage,
thus terminating the on-cycle (Figure 8).
peak-current comparator has only a 260ns delay.
V DD
PEAK-CURRENT
COMPARATOR
60mV
CLP
CSP
CSN
A V = 34.5
CA
g m = 550 μ S
CEA
MAX16818
SET
BST
EAN
EAOUT
VEA
RAMP
2 x f S (V/s)
CPWM
CLK
S
R
CLR
Q
Q
DH
LX
DL
Figure 8. MAX16818 Phase Circuit
SHDN
PGND
______________________________________________________________________________________
17
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